Recently, downsizing and weight saving are further demanded with respect to mobile electronic devices, such as mobile phones and PDA, on which display devices including liquid crystal display devices and organic electroluminescence displays are mounted. Along with this trend, downsizing of a non-opening part in a substrate for display device included in the display device, namely, frame narrowing of the substrate for display device has been developed.
Further, since a thinner device can be obtained at reduced cost, display devices equipped with full-monolithic substrates for display device are increasing, the full-monolithic substrates comprising peripheral circuits required for driving, such as driver circuits, formed thereon. In the display device equipped with a full-monolithic substrate for display device, a pixel-driving circuit formed on the substrate for display device increases a region for peripheral circuits (frame region). To overcome this, a multilayer wiring in which a wiring included in the peripheral circuit is routed in a multilayer structure has been developed so as to facilitate the frame narrowing.
The configuration of a conventional substrate for display device is described with reference to a drawing. FIG. 2 is a schematic cross-sectional view illustrating a conventional substrate for display device.
As illustrated in FIG. 2, a conventional substrate 1100a for display device comprises: a semiconductor layer 1102 including a channel region 1102a and high-concentration impurity regions 1102b, 1102c; a gate insulating layer 1103; a wiring layer 1121; an interlayer insulating layer 1131 including contact holes 1141a, 1141b; a wiring layer 1122; an interlayer insulating layer 1132 including a through hole 1142; a wiring layer 1123; an interlayer insulating layer 1133 including a through hole 1143; and a pixel electrode 1105, laminated in this order on a main face of a substrate 1101. In addition, the substrate 1100a for display device is equipped with a pixel transistor 1110 that is a top-gate type (planer type) thin-film transistor (TFT) comprising the semiconductor layer 1102, the gate insulator 1103, and a gate electrode 1104 formed on the channel region 1102a in the wiring layer 1121.
The contact hole 1141a is a connection hole penetrating the interlayer insulating layer 1131 and the gate insulating layer 1103 to electrically connect a lower connection wiring (lower wiring) 1107 positioned in a wiring layer 1122 to the high-concentration impurity region 1102b. The contact hole 1141b is a connection hole provided for electrically connecting a source wiring 1106 positioned in the wiring layer 1122 to the high-concentration impurity regions 1102c. The through hole 1142 is a connection hole penetrating the interlayer insulating layer 1132 to electrically connect an upper connection wiring (upper wiring) 1108 positioned in the wiring layer 1123 to the lower connection wiring 1107. Further, the through hole 1143 is a connection hole penetrating the interlayer insulating layer 1133 to electrically connect the pixel electrode 1105 to the upper connection wiring 1108.
The technical art for providing a wiring substrate having a small and high-performance functional circuit, in which, the multilayer wiring can be formed in few processes; and a semiconductor device includes a wiring substrate comprising: a first wiring formed on a substrate having an insulating surface; a first interlayer insulating layer covering the first wiring; a second wiring formed on the first interlayer insulating layer; a second interlayer insulating layer covering the second wiring; a third wiring formed on the second interlayer insulating layer; a first contact hole formed in the first interlayer insulating layer to electrically connect the first wiring to the second wiring; and a second contact hole formed in the second interlayer insulating layer to electrically connect the second wiring to the third wiring, wherein the third wiring is wider than the first and second wirings, the second wiring is wider than the first wiring, and the diameter or area of the second contact hole is larger than that of the first contact hole (see Patent Document 1, for example).
[Patent Document 1]
JP-A 2005-72573